How To Make A Generic Register File In Verilog

Verilog Blueprint of a Register File

Objective: In this lab exercise, yous volition utilize Verilog hardware description language to design and simulate a annals file, which will be used in after lab exercises. Verilog design provides an alternative to the annals file in schematic.

Register File Specification : A annals file consists of thirty-two 32-bit registers that tin can exist read and written by supplying a register number to be accessed. The figure 1 and effigy 2 testify you a typhoon schematic of the register file. The register file with two read ports and one write port has five inputs (Read register number 1, Read register number 2, Write register, Write data, and Write control), and 2 outputs (Read information one and Read data 2). Each of Read register number 1 (readreg1), Read annals number 2 (readreg2), and Write register (writereg) is used to specify one of the 32 registers for either reading or writing. The register file likewise has clock signal input clk and clear indicate input clr.

The write operation takes place on the falling edge of the clk point when the Write control (RegWrite) is logical one. The read functioning, however, is not clocked - it is combinational. Thus, the value of Read data 1 (read1) should e'er exist the contents of the annals specified by the Read register number ane. Similarly, the value of Read data 2 (read2) should always be the contents of the register specified by the Read annals number 2. The post-obit figure and table give the description of the register file. The table only describes the cases when clear point clr is 0. When the articulate betoken clr is 1, articulate the registers.

Input						Within of the register file	Output
clk	RegWrite	readreg1	readreg2	writereg	information	registers 0~31	read1	read2
		annals no. i					read the data from the register specified by readreg1
			register no. 2					read the data from the the register specified by readreg2
	0				data	no change
	1			register no.	data	write data into the register specified past writereg

Lab Requirements :

to become familiar with Sequential logic Verilog pattern, written report the Verilog code of positive (rising) edge-triggered D flip-flop with asynchronous articulate and Verilog code of negative (falling) border-triggered D flip-flop with asynchronous articulate. and Help for Sequential Logic Verilog.
to apply Verilog (either structural description or behavioral description) to design a register file with thirty-two 32-scrap registers described in Register File Specification. The registers in the register file can be alleged using an assortment. This is non required, but it is convenient way to reference the registers.
to debug the lawmaking, simulate the designed register file using stimulus file testfixture.new, and compare simulation event with the corrected result.
to write report in English. The written report must be typed and include the Verilog code with short comments and simulation results.

Help for Sequential LogicVerilog :

Read the Verilog code of positive (rising) border-triggered D flip-flop with asynchronous clear and Verilog code of negative (falling) border-triggered D flip-flop with asynchronous clear. The module and its inputs and outputs are declared. q is declared equally of type reg since it volition shop data. The procedure begins with the keyword e'er. Following is @(posedge clock or posedge articulate). The @ operator can be viewed equally "wait for result." This is the event control statement for the procedure that initiates procedure execution if an result, i.e., a specified change in a specified indicate occurs. For the D flip-bomb, if either clock or clear alter, then the process is executed. It is of import to note that the event control statement is not a parameter listing containing all inputs. For example, data does not appear, since a change in its value cannot initiate a possible modify in the value of data. Following the effect command statement at the beginning of the procedure is the keyword begin, and at the end of the process the keyword stop appears.

Within the body of the process, there are additional Verilog provisional structures that can appear. The general structure of an if-else in Verilog is:

if (condition) begin procedural statement stop
{else if (condition)
begin procedural argument stop}
{else
begin procedural statement end}

If there is a unmarried procedural argument, then the begin and stop are unnecessary.

The procedural statements are classified as blocking and non-blocking. Blocking assignments use = as the consignment operator and non-blocking assignments use <= equally the operator. Blocking assignments are executed sequentially, much like a programme in C programming linguistic communication. Non-blocking assignments evaluate the right mitt side, but do not make the assignment until all correct hand sides have been evaluated.

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